1. Field of the Invention
The present invention relates to a display having a display panel mounted there and a driving method of the display panel.
2. Description of the Related Art
Recently, a plasma display panel (hereafter, referred to as PDP) with a plurality of discharge cells arranged in matrix gains attention as a two-dimensional image display panel. The PDP is directly driven by a digital image signal and the number of the displayable brightness gradation is determined by the number of the bits of the pixel data for every pixel based on the digital image signal.
Subfield method is known as a gradation display method of the PDP. The subfield method features division of a display period into a plurality of sub-periods to drive each cell. In the subfield method, the display period of one field is divided into a plurality of subfields so to perform the light-emission drive on the PDP in every subfield. Each subfield includes an address period of setting a light-on mode or a light-off mode of each pixel depending on the pixel data and a light emission sustaining period for lighting on (emitting light) only the pixel in the light-on mode, for the period corresponding to the weight of the subfield. Namely, whether the discharge cell should emit light or not in each subfield is set in every subfield (address period), and only the discharge cell set at the light-on mode is made to emit light for only the period assigned to the subfield (light emission sustaining period). Thus, there occurs the case where a subfield in a light emitting state and a subfield in a light-off (non-light emitting) state exist in a mixed way, hence to visualize the intermediate gradation depending on the total sum of the light-emission periods of the respective subfields within one field.
FIG. 1 schematically shows an example of a light emission drive format of the PDP. For example, refer to FIG. 6 to FIG. 8 of Japanese Patent Kokai No. 2001-154630 (patent document 1).
Namely, one field in an image signal is divided into twelve subfields of SF1 to SF12 and the drive of the PDP is performed in each subfield. In this process, each subfield is formed by an address stage Wc for setting each discharge cell of the PDP at “light-on state” (namely, operative mode) according to an input image signal and “light-off state” (namely, non-operative mode) and a sustain stage Ic for making only the discharge cell in the “light-on state” emit light only for the period (the number of times) corresponding to the weight of each subfield. Here, a simultaneous reset stage Rc for initializing all the discharge cells of the PDP into the “light-on state” is executed only in the head subfield SF1, and an erase stage E is executed only in the last subfield SF12.
FIG. 2 shows pixel drive data GD obtained by performing the following conversion processing on the pixel data and its corresponding gradation and light-emission drive pattern of a discharge cell (for example, refer to the patent document 1).
By sampling an image signal, for example, the pixel data for 8 bits can be obtained. The obtained pixel data is subjected to the multiple gradation processing and while keeping the current number of gradation levels, the number of the bits is reduced to 4 bits hence to generate the multiple gradation-processed pixel data PDs. The multiple gradation-processed pixel data PDs is converted into the pixel drive data GD consisting of first to twelfth bits, according to a conversion table, as shown in FIG. 2. Each of these first and twelfth bits corresponds to each of the above-mentioned subfields SF1 to SF12.
FIG. 3 is a view showing the applying timings of various drive pulse to be applied to the row electrodes and the column electrodes of the PDP, according to the light-emission drive format shown in FIG. 2 (for example, refer to the patent document 1). FIG. 3 shows the case of the driving according to a selective-erasing method (one-reset one-select-erase address method).
In the simultaneous reset stage Rc of the subfield SF1, at first, the reset pulse RPx of negative polarity is applied to the row electrodes X1 to Xn. Simultaneously with the application of the reset pulse RPx, the reset pulse RPY of positive polarity is applied to the row electrodes Y1 to Y2. According to the application of the reset pulses RPx and RPy, all the discharge cells are discharged and reset, and each wall charge of the same predetermined amount is formed within each discharge cell. Thus, all the discharge cells are initialized into the “light-on state”.
In the address stage Wc of each subfield, pixel data pulses DP each having a voltage corresponding to a logical level of the pixel drive data bits DB1 to DB12. The pixel drive data bits DB1 to DB12 correspond to the first to the twelfth bits of the pixel drive data GD. For example, in the address stage Wc of the subfield SF1, at first, the pixel drive data bit DB1 is converted into a pixel data pulse having a voltage corresponding to its logical level. The number m of the pixel data pulses corresponding to the first line is defined as the pixel data pulse group DP11, the number m of the pixel data pulses corresponding to the second line is defined as the pixel data pulse group DP12, the number m of the pixel data pulses corresponding to the n-th line is defined as the pixel data pulse group DP1n, and each of the pixel data pulse groups DP11 to DP1n is sequentially applied to the column electrodes D1 to Dm.
Further, in the address stage Wc, at the same timing as each applying timing of the pixel data pulse group DP as mentioned above, a scanning pulse SP of negative polarity is sequentially applied to the column electrodes Y1 to Yn. In this process, only the discharge cell at an intersection of the row electrode having the scanning pulse SP applied and the column electrode having the pixel data pulse of high pressure applied, is discharged (selective-erase discharge) and the wall charge left within the discharge cell is selectively erased.
According to the selective-erase discharge, the discharge cell initialized into the “light-on state” in the simultaneous reset stage Rc is turned to the “light-off state”. While, the discharge cell where the selective-erase discharge does not occur is maintained in the initialized state, namely in the “light-on state” in the simultaneous reset stage Rc.
In the sustain stage IC of the respective subfields, as illustrated in FIG. 3, respective sustain pulses IPX and IPY of positive polarity are alternatively applied to the respective row electrodes X1 to Xn and Y1 to Yn. Here, in the sustain stage IC, the sustain pulse IP is applied in such a manner that the number of the sustain pulses IP may become a predetermined ratio in the respective subfields SF1 to SF12. For example, as shown in FIG. 1, the ratio of the number of the sustain pulses in the respective subfields becomes    SF1:SF2:SF3:SF4:SF5:SF6:SF7:SF8:SF9:SF10:SF11:SF12=1:2:4:7:11:14:20:25:33:40:48:50.
In this case, only the discharge cell where the wall discharge is still left, namely the discharge cell set at the “light-on state” in the above address stage Wc, is sustained every time the sustain pulses IPX and IPY are applied there. Accordingly, the discharge cell set at the “light-on state” sustains the light emission state accompanying the sustain discharge, for the number of the times assigned to each subfield as mentioned above.
The erase stage E is executed only in the last subfield SF12. In this erase stage E, an erase pulse AP of positive polarity is generated and applied to the respective column electrodes D1 to Dm. Further, simultaneously with the applying timing of the erase pulse AP, the erase pulse EP of negative polarity is generated and applied to the respective row electrodes Y1 to Yn. The simultaneous application of these erase pulses AP and EP causes the erase discharge in all the discharge cells in the PDP and extinguishes the wall charges left within all the discharge cells. According to the erase discharge, all the discharge cells in the PDP are turned to the “light-off state”.
In the drive method as mentioned above, only in one of the subfields, only the discharge cell in a light emission state in the proximate subfield is selectively erased in the address stage. Thus, starting from the head subfield, the number N (for example, 12) of the subfields are sequentially lit on, hence to display the N+1-level gradation (for example, 13-level gradation), and then, the gradation display depending on the brightness represented by an input image signal is realized according to the total sum of the sustain discharges in the respective subfields.
In the driving of the PDP, however, the reset discharge and the address discharge accompanied by the light emission not related to the display image should be generated, in addition to the sustain discharge serving for a display image. Accordingly, it has the defect of deteriorating the contrast of an image, especially, the dark contrast at a display time of an image indicating a dark scene.
In order to solve the above problem, an object of the present invention is to provide a display and a driving method of a display panel capable of improving the dark contrast.